1. Field of the Invention
The present invention relates to a MOSFET transistor having a channel region composed of different impurity concentration regions.
2. Description of the Background Art
In FIG. 1, there is shown a conventional N-channel MOS transistor which comprises a P-type semiconductor substrate 1, an N-type polycrystalline silicon gate electrode 3 formed on the surface of the substrate 1 via a gate insulating oxide film 5, and a drain 7 and a source 9 formed in the surface area of the substrate 1 in the right and left sides of the gate electrode 3.
In this case, in order to determine a threshold voltage to a relatively large value such as approximately 0.6 to 0.8V, it is necessary to fairly raise the concentration of the P-type impurity in the substrate 1. That is, when polycrystalline silicon implanted with an N-type impurity is used for the gate electrode 3, since the work function difference between the substrate 1 and the gate electrode 3 becomes large, the impurity concentration in the substrate 1 is necessarily increased so as not to form an inversion layer in a channel region 11 in the surface area of the substrate 1 between the drain and source regions 7 and 9.
On the other hand, when the gate oxide film 5 is thinned as the device is miniaturized, the impurity concentration in the substrate 1 must be increased in order to obtain a large threshold voltage. That is, even when the device is miniaturized, the reduction of the threshold voltage causes the increase of the leakage current, and hence the threshold voltage can not be reduced largely. Accordingly, as the device is miniaturized, the impurity concentration in the substrate is increased.
As described above, the impurity concentration increase in the substrate invites the fall-off of the carrier mobility. That is, when the impurity concentration in the substrate is increased, the electric field in the direction perpendicular to the substrate increases to cause the carrier dispersion in the surface area and the impurity dispersion due to the impurity concentration increase which affect the fall-off of the carrier mobility. Further, the impurity concentration increase in the substrate brings about the increase of the variation rate of the threshold voltage increase (back bias effect) while a reverse bias is applied between the source and substrate, thereby lowering the characteristics of the device. Further, it becomes difficult to operate the device in high speed, and the current driving ability thereof is reduced.
Meanwhile, when the gate electrode 3 is made of a metal having a high melting point, a silicide thereof or an undoped polycrystalline silicon, the work function difference between the substrate 1 and the gate electrode 3 becomes small, thereby enabling the reduction of the impurity concentration in the substrate even when the large threshold voltage is obtained.
However, in such a case, the depletion layer is liable to extend from both the drain and source regions 7 and 9 toward the channel region 11. Hence, when the depletion layers extending from the drain and source regions 7 and 9 are contacted with each other, a short-circuit is caused between them to cause the punch-through phenomenon. Also, even when such depletion layers do not contact with each other, the depletion layers extending in the channel region 11 bring about the short channel effect.
In order to prevent or minimize such punch-through phenomenon and short channel effect, p pocket regions are provided in the surface area of the substrate between the ends of the gate elecrode and the drain and source regions, as disclosed in the documents "IEDM 82 Tech Digest (1982), pp 718-721, Seiki Ogura et al,".
In FIG. 2, there is shown a conventional N-channel MOS transistor having p pocket regions 13 in the surface area of the substrate 1 between the ends of the gate electrode 3 and the drain and source regions 7 and 9. The p pocket regions 13 implanted with an N-type high concentration impurity are formed in a deep position under silicon oxide (SiO.sub.2) side walls 15 on the gate electrode 3 between the drain and source regions 7 and 9 by using a technique for providing such side walls 15. The p pocket regions 13 function so as to restrain the extension of the depletion layers from the drain and source regions 7 and 9, thereby preventing the punch-through.
In such a case, since the p pocket regions 13 are formed of a P-type high concentration region and become highly resistant, when the p pocket regions 13 are formed right under the side walls 15, the driving force of the device is reduced, and a high electric field is produced in the channel region 11 to generate hot electrons. Therefore, the p pocket regions 13 should be formed in a deep position below the surface area of the channel region 11.
As described above, in any of the conventional MOS transistors, it is quite difficult to effectively improve the high speed operation of the device and the current driving ability and to effectively prevent the punch-through phenomenon and the short channel effect.